1. Field of the Invention
The present invention relates generally to semiconductor devices and, more particularly, to a semiconductor package which includes a metal lid coupled to one or more prescribed metal features of the leadframe of the package to form a shield that effectively surrounds the active circuitry, thus creating a type of Faraday shield.
2. Description of the Related Art
Semiconductor dies are conventionally enclosed in plastic packages that provide protection from hostile environments and enable electrical interconnection between the semiconductor die and an underlying substrate such as a printed circuit board (PCB) or motherboard. The elements of such a package comprise a metal leadframe, an integrated circuit or semiconductor die, bonding material to attach the semiconductor die to the leadframe, bond wires which electrically connect pads or contacts on the semiconductor die to individual leads of the leadframe, and a hard plastic encapsulant material which covers the other components and forms the exterior of the semiconductor package, commonly referred to as the package body.
The leadframe is the central supporting structure of such a package, and is typically fabricated by chemically etching or mechanically stamping a metal strip. A portion of the leadframe is internal to the package, i.e., completely surrounded by the plastic encapsulant or package body. Portions of the leads of the leadframe may extend externally from the package body, or may be partially exposed therein for use in electrically connecting the semiconductor package to another, external component. In certain semiconductor packages, a portion of the die pad of the leadframe also remains exposed within the package body. Additionally, in other semiconductor package designs, the leadframe is substituted with a laminate substrate which includes conductive patterns adapted to facilitate the electrical connection thereof to both the semiconductor die and an external component. Still further, other semiconductor package designs such as cavity packages and hermetic packages often include a metal lid attached to other prescribed portions thereof, such as the package body of the package.
As the art has moved to smaller, lighter weight, and higher frequency electronic devices such as cellular telephones, semiconductor packages utilized in these electronic devices are increasingly placed closer to other electronic components and structures. Due to this reduced spacing, electromagnetic interference (EMI) or radio frequency (RF) radiation emanating from a semiconductor package has a greater probability of interfering with the normal operation of an adjacent electronic component, and vice-versa. In this regard, many applications using semiconductor packages that incorporate a metal lid (e.g., the cavity packages and hermetic packages described above) often also require a modality for shielding the active circuitry contained in the package from the effects of EMI and/or RF interference. As indicated above, in some applications, the shield is required to prevent the active circuitry contained within the package from emitting frequencies or “noise” that might affect the performance of the application or other components therein.
To prevent such unacceptable EMI and/or RF interference, it is known in the prior art to add one or more shields (often referred to as “cans” or “cages”) to an application during the board level assembly process. These shields are typically attached to an underlying support structure such as a printed circuit board (PCB) to provide EMI/RF shielding to the electronic component(s) covered thereby. Though these shields are available in multiple designs and shapes, they are not always as effective as desired, and can further add as much as 15% to the overall manufacturing cost of the device depending upon the design and device performance specifications thereof. As a result, the inclusion of the shield(s) in the application typically adds cost, complexity, and support issues thereto. Still further, the efficacy of shielding cages is typically limited since such cages typically do not share an on-die or interior package reference ground. In this regard, establishing a common ground potential with a circuit device depends upon the PCB ground plane design and interconnect via technology utilized, as well as the solder joints of the package to the board.
Another technique employed in the prior art to prevent EMI and/or RF interference involves the use of conformal, conductive coatings. More particularly, in accordance with this technique, the entire package is coated with an impregnated conductive material such as Ag that is electrically connected to the ground reference of device. However, this technique does not work with MEMS devices or those requiring an external port or opening in the top or bottom of the package.
Yet another prior art technique to prevent unacceptable EMI and/or RF interference involves the application of a conformal shielding material to the package body of a semiconductor package, and establishing electrical communication between the shielding material and contact points on a prescribed surface of the package through the use of wires which extend through and protrude from the package body. However, this particular technique is limited to over-molded semiconductor packages and to those that have sufficient interior space to add those internal wires which facilitate the electrical communication with the shielding material. Moreover, such wires must be interstitially spaced around the perimeter of the semiconductor package well as between other components if included in the interior thereof.
Thus, in the case of molded semiconductor packages that incorporate a lid, there are no known shielding techniques currently applied beyond conformal coatings, or the can and cage techniques described above. The present invention addresses this issue by allowing for the use of the lid as a shield that effectively surrounds the active circuitry, and thus forms a type of Faraday shield. In accordance with the present invention, the lid is coupled to a metalized area located on the surface of the active circuitry, or to an additional metalized die. Appropriate interconnect methods between the lid and the metalized die or metalized area include, but are not restricted to, wire bonding, bumps, tabs, or similar techniques. As such, the present invention provides a unique approach to addressing EMI and/or RF interference in that it contemplates the utilization of a metalized area located on the surface of the die as a feature of the die, or as a redistribution layer (RDL) of a prescribed shape added to the die surface, or as a separate metalized die stacked on the surface of an active circuit or adjacent thereto. These, as well as other features and advantages of the present invention will be discussed in more detail below.
Common reference numerals are used throughout the drawings and detailed description to indicate like elements.